APE2 digital signal processor

The APE2 configurable DSP processor is ideal for the low power, low gate count implementation of DSP algorithms in the data path. APE2 has been proven in software radio and other applications, and is often used as a co-processor for the XAP family.

The flexibility of the APE2 speeds time to market, by removing the need for custom hardware development and introducing programmability for signal processing. The APE2 provides a low risk solution. Its flexibility allows its hardware to be configured for the precise application requirement. Using the APE2 toolkit and starting from Matlab, developers will configure a DSP for their application, choosing from a wide range of arithmetic modules. The toolkit then generates the Verilog implementation.

The APE2 DSP has a parallel modular structure, with modules selected from a library of processing blocks. Any combination of modules can be selected to optimise the processor for a particular application. Data is passed between modules using the APE2 data routing bus. This unique design means that the output of any module is available at the input of any module.

The APE2 has VLIW (very long instruction word) architecture for maximum flexibility. Coupled with code compression tools, this will optimise program length. Parallel execution produces high performance, and the unique data routing bus ensures that all modules are kept fed with the data they need for non-stop signal processing.

Any number of modules can be selected to form an APE2 using the toolkit. The selection of modules can be easily changed during the development process to meet changing requirements. The toolkit provides usage statistics to enable the designer to reach an optimal solution. The ability to change the structure of the processor allows the designer to make tradeoffs between silicon area, processing speed and power consumption.