XAP4 and XAP5 processor cores
Powerful ASIC processor IP core solutions featuring:
• Low energy
• Low cost
• Low risk
• Very high code density
• Best in class performance
• Protected software operation
Our new XAP® processor cores are Von Neumann RISC processors, combining high code density and excellent performance with simplicity of memory system design and protected software operating modes. XAP processors apply the best-performing RISC design strategies and ASIC designers have a choice of processors; XAP4 for smaller applications addressing up to 64 kBytes, and XAP5 for applications with larger programs and data up to 16 MBytes. Use the Literature links on the right of this page to access the processor data sheets.
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Optimised for your application
XAP processors are designed for applications that require efficient data processing with low energy consumption at low cost. Choice of processor is determined by the memory system, which is governed by the application’s program size and data requirements. XAP’s high code density and 16-bit register width minimises both program and data memory size and cost. Registers are automatically paired when 32-bit data is processed or a 24-bit address is being calculated. XAP processors possess additional features to optimise security and reliability, especially with non-volatile memories such as Flash or OTP, as well as ROM and RAM.
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Efficient hardware
The XAP processor IP is delivered as a soft core in Verilog RTL, giving licensee’s full control over simulation and synthesis to optimise die area and power consumption. XAP Verilog also targets FPGAs for verification. A typical XAP-powered mixed-signal ASIC diagram is shown here.
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Notice how the unified data and address bus minimises the number of memory blocks required in a low-cost, low energy, mixed-signal ASIC with program instructions and constants being stored in a single memory.
XAP hardware includes an Interrupt Vector Controller, a Memory Management Unit and a SIF debug interface. ASIC designers expand the IVC and the MMU according to their system requirements, dealing with a variety of prioritised and nested interrupts and designing memory and i/o maps with access controlled by the processor’s mode.
XAP family roadmap
Cambridge Consultants has been designing processor cores since the early 1990s and this roadmap also shows our earlier XAP processors. XAP has been used in Bluetooth products from CSR (Cambridge Silicon Radio), ZigBee products from Ember Corporation, touch-screen control ASICs from 3M and many other chip designs. More than a billion XAP processors have now been shipped in silicon.
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The XAP architectures developed to follow semiconductor industry progress according to Moore’s law. Our first processors used Harvard architecture to achieve adequate performance on older 0.5 and 0.7 µm processes with programs fixed in ROM. Now, the latest XAP4 and XAP5 target mixed-signal process geometries of 0.18 or 0.13 µm, or advanced digital processes at 90 nm and below, with programs stored in modern Flash or OTP non-volatile memory. Their Von Neumann architecture offers a more efficient design and facilitates remote software upgrades throughout a product’s life-cycle.
Web resources
A more detailed background paper describing the XAP processors and trial versions of xIDE for selected XAP processors are available via the link to downloads on the right.
Information on XAP processor IP is also available on other web sites:
